1. Field
Embodiments of the invention relate to memory testing.
2. Background Information
It may be beneficial to test memory arrays in order to detect faults, such as, for example, stuck-at faults, addressing faults, coupling faults, neighborhood pattern sensitive faults, indepotent faults, and the other faults. A variety of memory array testing protocols are known in the arts.
Certain protocols, such as, for example, deterministic marches, rely on an understanding of the physical topology of the memory array. However, such information about the memories may be confidential or otherwise unavailable, and this may adversely affect the deterministic tests.
Other protocols recognize that the topology may not be known and apply random address generation, random data, and random reads and writes. However, such tests may involve excessive test times and complicated test failure diagnostics. Additionally, such tests may have limited ability to test for addressing faults, since there may not be predictable reads and writes to the same address.